1. Field of the Invention
This invention relates to applying a post-hot metal deposition process to semiconductor wafer manufacturing, in order to increase the size of grain structures and improve electromigration resistance in semiconductor devices.
2. Description of the Related Art
Currently, in the manufacturing of semiconductor devices, the process of filling in contact voids with a conductive metal layer is done using conventional etching techniques and pillar techniques. Conventional etching techniques using Aluminum (Al) are well known in the art for applying a conductive pattern to a semiconductor device. Conventional pillar techniques fill in contacts on the semiconductor device with seed material, such as Titanium. Such conventional pillar techniques are very complicated, and result in very expensive deposition procedures.
In a conventional pillar technique, a seed material is deposited onto a substrate. Next, a layer of tungsten is deposited on top of the seed material. Some amount of tungsten must be ground off of the seed material at this stage to arrive at the proper thickness of tungsten on the seed material. As a result, the pillar technique is an expensive and time consuming process for depositing a conductive layer onto a semiconductor substrate and for filling in contact voids on the semiconductor substrate.
A conventional method of etching copper (Cu) onto a substrate is to first put down a very thick oxide image at locations where the copper conductor will be placed onto the substrate. An oxide path is opened up and copper is deposited onto the oxide image. The copper is then ground down all the way to the top of the oxide image where the conductor opening is located. Like the pillar techniques described above, this etching technique is also very complex and expensive.
Since copper has about twice the conductivity of Aluminum, copper as a conducting material for semiconductor ICs is becoming more desirable. The small sizes of IC components make this higher conductivity a useful characteristic. However, conventional techniques for applying copper onto semiconductor substrates present many problems, since Cu cannot easily be etched onto semiconductor substrates. Currently, there is no way of keeping the resistance of the Cu metal viable throughout the etching of the Cu onto the semiconductor substrate.